1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to the layout of ESD protection elements used in a semiconductor chip.
2. Description of the Related Art
Recently, demands for portable electronic devices such as mobile telephones, portable information processing terminal devices and small audio devices have been rapidly increasing.
In order to meet these demands, attempts are made to reduce the size, weight and thickness of a semiconductor device.
Therefore, in semiconductor devices, use is made of a system-on-chip (SOC) technique in which a plurality of systems are stored in one semiconductor chip and a multi-chip package (MCP) technique in which a plurality of semiconductor chips such as LSI chips or memory chips are stacked on one package substrate.
The LSI chip has a plurality of pads which are connected to the external terminal of the package substrate. In the LSI chip, a power supply circuit having an electrostatic discharge (ESD) protection element with predetermined ESD resistance is connected to a substrate pad or a power supply ring on the package substrate via a bonding pad or wire.
Thus, internal circuits in the LSI chip are protected against an ESD breakdown current.
Recently, the miniaturization of a MOS transistor has been carried out, and the ESD resistance of the gate oxide film of the MOS transistor keeps decreasing. Therefore, the size and number of the ESD protection elements in the chip tend to be increased in order to ensure ESD resistance sufficient to prevent the breakdown and defect of the LSI chip.
In products with high power consumption, a large number of power supply terminals are used, and the size and number of the ESD protection elements are therefore increasing. Moreover, a plurality of ESD protection elements are provided in various places within the chip in consideration of the wiring layout on the package substrate.
This increases the size of the semiconductor chip, and it is difficult to make the chips and a package device using these chips smaller.